The present invention relates to a thin-film multilayer wiring board for being packaged in electronic devices or various types of electrical apparatus, and a process for producing such a wiring board.
For elevating the operating speed of computers, increase of signal transmission speed of the packaging module is an important factor.
Hitherto, a thick-film board comprising a ceramic substrate and a wiring layer principally made of W or Mo and formed on said ceramic substrate by a laminating and sintering method has been used as said module. Recently, however, attention is focused on a thin-film multilayer wiring board in which, in order to realize speed-up of signal transmission, a polyimide film with a low dielectric constant is formed as an interlaminar insulating film on the ceramic substrate, and a conductive layer is made of a highly conductive substance such as Cu, Al, Au or the like.
In recent years, however, computer performance has advanced rapidly and the number of the packaged gates has increased remarkably, entailing the necessity of increasing the number of the wiring layers in the thin-film wiring system.
Several proposals have been made on the thin-film multilayer wiring techniques, wherein a successive laminating system is generally employed. This system comprises forming a conductor layer made of Cu, Al or the like on a ceramic or Si substrate, forming via holes therein, conducting insulating layer patterning by photolithography, and making electrical connections.
Techniques for forming via holes or through-holes of 100 .mu.m or less in diameter are needed for said interlaminar connection. Also, fine patterns with a line width or space width of 20-50 .mu.m are necessary for thin-film wiring. For instance, it is required to lay 2-5 wires between the 150-500 .mu.m connecting pads. In this case, the via hole diameter needs to be about 20-30 .mu.m. However, the limit of the hole diameter that can be formed by the currently available drilling techniques is about 70 .mu.m, and other means must be applied for forming the holes of smaller diameters.
Recently, attention is drawn to laser working and dry etching as suitable methods for forming fine holes such as mentioned above. Both methods are excellent in fine working, but a difference is seen between them in shape of the holes formed.
It is known that the method using excimer laser is an excellent working method for forming fine via holes or through-holes (JP-A-60-261685). However, he projected shape of the hole formed thereby tends to taper down toward the end (base) with an angle of about 20 to 30.degree. against the axis of the hole.
As a method that can eliminate the above problem, a so-called conformal mask method--a method in which laser working is performed through a mask comprising a metallic film having openings at the pattern portion of an organic insulating layer where holes are to be formed--is effective. According to this method, as shown in FIG. 2, the hole formed has a taper angle (.theta.) of about 15-5.degree. against the axis of the hole when the energy density of the excimer laser is 300 to 1,000 mJ/cm.sup.2. Thus the tapering phenomenon toward the end (base) can be suppressed to a considerable degree. The result of the tests conducted by the present inventors shows that the taper angle .theta. of the hole formed is reduced and its straightness is enhanced proportionally as the energy density increases.
On the other hand, as opposed to said laser working, according to dry etching using oxygen plasma controlled to a low gas pressure (for example, 5 Pa or less), it is possible to form an almost straight hole with a taper angle (.theta.) less than 5.degree.. It was found from a series of experiments that when the plasma gas pressure becomes higher than 5 Pa in dry etching of an organic insulating layer such as a polyimide layer, the hole formed is curved in section like a barrel.
Such drying etching techniques have been used for wiring or patterning of the insulating layers in the LSI semiconductor manufacturing processes. For instance, a method for forming the contact holes in the interlaminar insulating layer on a semiconductor substrate by dry etching using a reactive gas (a mixed gas of CF.sub.4, CHF.sub.3, Ar, O.sub.2, Cl, etc.) is disclosed in JP-A-4-150023 and JP-A-5-121371. In the former, the etching gas pressure for forming a straight hole is specified to be 0.6 Torr or below (80 Pa or below) while in the latter, the etching gas pressure is defined to be 10 to 50 m Torr (1.33 to 6.65 Pa).